-- $Id$

-- Copyright (C) 2008-2009 FAUmachine Team <info@faumachine.org>.
-- This program is free software. You can redistribute it and/or modify it
-- under the terms of the GNU General Public License, either version 2 of
-- the License, or (at your option) any later version. See COPYING.


library ieee;
use ieee.std_logic_1164.all;
ENTITY test_bench IS
END ENTITY test_bench;

ARCHITECTURE test_bench_impl of test_bench IS
	signal s : std_logic;
BEGIN
	p : process
	begin
		s <= '1';
		wait on s;
		s <= '1' and (not s);
		wait on s;

		assert s = '0' report "not (stdlogic)" severity failure;
		assert false report "simulation finished" severity note;
		wait;
	end process;
END;
